1. Field of the Invention
The present invention relates to a clock distribution circuit and a layout design method using the same.
2. Description of Related Art
In LSI (Large Scale Integration) layout design in recent years, as the operating frequency has increased to implement more sophisticated functions, the demand for the increase in accuracy of the signal duty ratio has been grown. In a system in which both rising and falling edges of a clock signal are used, in particular, securing set-up times and hold times of a flip-flop and the like, for example, becomes more difficult as the deviation of the signal duty ratio from 50% becomes larger. Further, in the case of high-frequency signals, the pulse width cannot be secured due to the delay of the rising-edge and falling-edge waveforms. Therefore, it has been desired to adjust the duty ratio of an output signal in such systems.
FIG. 8 shows a clock tree circuit disclosed in FIG. 6 of Japanese Unexamined Patent Application Publication No. 2002-269166. As shown in FIG. 8, the duty ratio of an output signal from a clock tree circuit is adjusted by preparing a plurality of duty ratio adjustment cells 13 having mutually different characteristics, and inserting a proper duty ratio adjustment cell 13 at the first stage of the clock tree circuit in Japanese Unexamined Patent Application Publication No. 2002-269166. Specifically, six types of duty ratio adjustment cells 13 having mutually difference characteristics, for example, are prepared. Then, the duty ratio of a clock tree circuit is adjusted by selecting one of the duty ratio adjustment cells 13 according to a desired duty ratio and inserting the selected duty ratio adjustment cell 13 at the first stage of the clock tree circuit.
FIG. 9 shows a circuit diagram of a duty ratio adjustment cell 13 disclosed in FIG. 7 of Japanese Unexamined Patent Application Publication No. 2002-269166. As shown in FIG. 9, when a duty ratio adjustment cell 13 is driven by two transistors, its switching action becomes faster compared to the case of driving the duty ratio adjustment cell with one transistor. Therefore, it is possible to create a delay difference between the rising edge and the falling edge by cutting off the line C1 or C2.